This invention relates to the application of a system clock to a plurality of selectable modules that process the clock signals at different rates. In one example, the modules process test and debug signals, such as IEEE 1149.1 clock (and associated information), at different clock rates.
In certain processing units, different modules can process input signals at different clock rates. For example, modules of certain ARM Corporation processing units process test and debug signals at different rates depending on the module. In the JTAG test and debug format, not only is a clock (CLK) signal required, but a return clock (RCKL) signal must be present.
Referring to FIG. 1, a system having a plurality of modules processing data groups at different rates is illustrated. The processing system includes modules 1-N. Each module has a (system) CLK signal applied to an input terminal thereof. Each module processes data at a rate that is module-dependent. When the processing of the data is complete, the modules generate RCKL(1) through RCKL(N) signals. In FIG. 1, the application of test data in TDI(1) through test data in TDI(N) to the modules is illustrated. After processing, the test data out TDO(1) through test data out TDO(N) is retrieved from the modules. In the important JTAG example, the TDI(1) through the TDI(N) are applied, by means of a chain configuration, to the modules and the TDO(1) and TDO(N) are retrieved series format from the modules through a chain configuration. Consequently, it is necessary that the system clock signal be consistent with any of the RCLK(h) signals. Expressed in another manner, the TDI(k) are entered in the module, processed during a period of time determined by the design of the module, and retrieved from the modules for analysis.
As will be clear, either through failure of the system clock or as a result of variations in the time to process the data signals entered into each module, a timing error will occur.
In a typical test procedure, not all of the modules of the processing unit may be the subject of a particular test procedure. To include those modules might compromise the test procedure or reduce the speed with which the test and debug procedure can be performed.
It is therefore a feature of the apparatus and associated method to perform a test and debug procedure on selected modules of a processing system. It is yet another feature of the apparatus and associated method to determine when a return clock signal is not consistent with system clock signal during a test and debug procedure of processing unit having selectable modules. It is a more particular feature of the apparatus and associated method to generate return clock negative edge and positive edge signals for use in generating a composite RCL signal. It is yet another particular feature of the apparatus and associated method to apply RCLK_NE (Return clock negative) signal and RCLK_PE Return clock positive) signal from selected modules to an adder circuit, the RCLK_NE and RCLK_PE signals being synchronized with the module RCLK signal. It is still a further feature of the present invention to apply RCKL_NE and RCLK_PE signals continuously to the adder unit for the deselected modules. It is yet another particular feature of the present invention to provide a seamless transition between the selection and the deselection of a module.